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SETSCI - Volume 1 (2017)
ISMSIT2017 - International Symposium on Multidisciplinary Studies and Innovative Technologies, Tokat, Turkey, Dec 02, 2017

Design of DFT Algorithm and Realization by Using FPGA (ISMSIT2017_43)
Kürşad Uçar1*, Hasan Erdinç Koçer2
1Selcuk university, Konya, Turkey
2Selcuk university, Konya, Turkey
* Corresponding author: kucar@selcuk.edu.tr
Published Date: 2017-12-08   |   Page (s): 183-187   |    136     5
ABSTRACT Field Programmable Gate Arrays (FPGAs) are configurable logic semiconductor devices which connect by programmable interconnections. They can be reprogrammed to desired application or functionality requirements. VHDL is a one of the hardware descriptive languages that use for changing the structure of the FPGA hardware. With DFT, discrete time data sets converts into a discrete-frequency representation, so this procedure provides a process of fast programming that often uses in signal processing. In this study, a design for processing DFT proposes. A 16 point DFT algorithm wrote using VHDL. The inputs of the design are 32 bit single precision floating numbers, these input points processed by Cooley-Tukey DFT algorithm and as a result 16 points complex numbers which are again in single precision floating point format obtained. During the processing of the data, Random access memory (RAM) element and pipeline registers are used for storing of the intermediate values. DFT operation conducted in three stages and each of the stage work parallel to other. Developed VHDL code realized physically by using Altera FPGA board.  
KEYWORDS FPGA, VHDL, DFT, Pipeline
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[3] J. W. Cooley, and J. W. Tukey., An Algorithm for Computation of Complex Fourier Series, Mathematics of Computation, 1965.

[4] Brigham, E. Oran, The fast Fourier transform and its applications. Englewood Cliffs, N.J.: Prentice Hall, 1988.

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